Figure 4: Basic test flow for multi-die IC devices. See a basic multi-die IC test flow in Figure 4. probably good die) are extremely important yield criteria for multi-die ICs and raise the importance of in-depth probing (without reporting any false positives or negatives) of every die. The second speaker, Jerry Broz, SVP of Technology Development at International Test Solutions (ITS) in Reno, demonstrated his company’s contribution to cleaning wafer probe-cards, also outlined how ITS cleans test sockets for fully packaged units.īecause the final yield of a multi-die IC is the product of all building blocks’ yields (BB1 yield x BB2 yield x BB3 ….), very thorough probing of every die is essential – to achieve high-yielding multi-die IC devices. His entire presentation has been recorded and can be viewed here. (Courtesy: Ansys)Īfter giving this overview of multi-disciplinary design challenges, Kim presented and explained several 2.5D design examples that showed how Ansys tools and methodologies address power integrity (PI), electrical-thermal-mechanical interactions, and Signal Integrity (SI). Figure 3: Ansys chip – package – system design solutions in a supply-chain context. Figure 3 shows Ansys tools in this context and emphasizes again the importance of modeling and simulation of multi-physics building blocks. In addition to many technical topics, Kim also addressed the value of Ansys chip-package-system capabilities within the electronic supply chain. Figure 2: Ansys multi-scale and multi-physics design solutions for single and multi-die ICs (Courtesy: Ansys) This slide also emphasizes the importance of accurate models, to get meaningful simulation results and lists several models Ansys tools can generate, as foundations for accurate and comprehensive multi-physics simulations, at different abstraction levels. ![]() In Figure 2, Kim highlighted that Ansys offers solvers for a wide range of dimensions: from nanometers for transistors to centimeters for system-level simulations. Exhaustive multi-physics verification with the right EDA tools, using accurate models of building blocks as inputs, is the fastest and lowest-cost path to success. Building in enough margin “to make it work without using EDA tools” is not practical anymore, nor economical. Personal comment: This slide should give people who still think “I have a lot of experience and can rely on prototyping” some food for thought. Today’s multi-die IC designs include many millions of transistors, even may contain tens of billions of transistors and take 100s of person-months and many millions of dollars to develop. Kim explained that several decades ago, the functionality of designs with tens of transistors could simply be implemented and verified manually by experienced humans. Figure 1: Increasing chip design challenges – to be addressed by EDA tools. He gave a great overview, showing the value of electronic design automation (EDA) tools (Figure 1) then focused on Ansys’ broad range of modeling and simulation tools for 2.5D building blocks and chip – package – system co-design. Sooyong Kim, Sr Product Manager for 3DIC CPS (Chip-Package-System) delivered Ansys’ presentation, titled “Multi-disciplinary Simulation for 2.5D/3DIC Co-Design”. Modeling and Simulation of Multi-die IC Designs Two Knowledgeable speakers from Ansys and International Test Solutions (ITS) outlined their company’s technical capabilities and explained the value these tools and methodologies provide for multi-die IC design and test. On May 20 MEPTEC’s Executive Director, Ira Feldman, moderated another informative MEPTEC & iMAPS webinar.
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